NXP Kinetis KE06 SysTick Clock Source

Published by Tim Allen on 15th May 2018

Over recent months we have started to adopt the ARM Cortex-M based NXP (formerly Freescale) Kinetis processors for most of our new designs. While developing the software for an embedded system using the MKE06Z128 we wanted to use the ARM SysTick timer. According to § 3.3.1.3, ‘System Tick Timer’, of the KE06 Reference Manual (MKE06P80M48SF0RM Rev 3), the CLKSOURCE field in the SysTick Control and Status register selects either the core clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock (when CLKSOURCE = 0).

This feature is in common with a number of other Kinetis processors we have used. However, during testing, it became clear that with CLKSOURCE = 0, a divide-by-8 of the core clock is selected. NXP have confirmed this and at some point either the Reference Manual or the silicon will be updated.

It’s worth noting that the NXP CMSIS SysTick_Config() function always sets CLKSOURCE to 1, by setting SysTick_CTRL_CLKSOURCE_Msk in SysTick->CTRL, so much code may never have tried a CLKSOURCE of 0. This possibly explains why the fault has not previously been reported to NXP.

__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
  {
    return (1UL);                                                   /* Reload value impossible */
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
}

Categories: Development